Will Tang

Senior Layout Mask Design Engineer with 15+ years of experience in physical / mixed-signal design and chip implementation. Proficient in EDA tools such as Cadence Virtuoso XL and Calibre. Extensive experience in IP layout block design, including bandgap, DAC, ADC, PLL, oscillator, comparator, Schmitt trigger, LDO, buck converter, charge pump, HS/LS driver and flash memory. Experience in developing schematic / layout generator using SKILL script.

Solomon SystechLimited, Senior Physical Design Engineer

Jun 2025 - Oct 2025   (4.5 months)

• LCD display driver layout design using NEXCHIP 90nm fabrication process, achieving a 4% reduction in bandgap IP block.
• Got familiar with company physical verification / tapeout flow, SYSTEM ESD and latchup best layout practices.
• This role was discontinued due to organizational budgetary constraints.

Jan 2018 - Mar 2025   (7 years and 3 months)

• HV-product layout design using Vanguard 0.5um SOI 10V_200V, Supertex BIC9L 1um BCD 200V,

Atmel 77K 150nm SOI 1.8V_3.3V_5V_120V, TSMC 0.18um GenII BCD 1.8V_3.3V_5V_32V fabrication processes,

achieving Level-0LVS cleanliness and validating bond wire integrity using PIM tools.

• Custom layout:

bandgap, DAC, ADC, PLL, oscillator, comparator, Schmitt trigger, LDO, buck converter, HS/LS driver, BEMF

• Enhanced layout reliability and performance through EM/IR analysis with EAD and Totem.
• Prepared verification databases and checklistfor GDS stream-out process, executedphysical verification (ANT, DRC, LVS, 

PERC, PEX) with Calibre and Assura, and built IP macros using IPGenX to support reusable design components.

Nov 2012 - Dec 2017   (5 years and 2 months)

• VoIP SIP phone HW and SW (C-language) development with Wifi, GigabitEthernet, TFT touch LCD feature.

Jul 2005 - Oct 2012   (7 years and 4 months)

• MCU embedded NOR flash memory IP macro mixed-signal design using Fujitsu 0.35um, 0.18um, 90nm fabrication processes.
• Mixed-signal design with custom layout:

Flash memory core array, XY decoder, voltage booster, charge pump, bandgap, comparator, oscillator, testmode circuit

Aug 2003 – Jun 2004   (11 months)

• Characterized and optimized memory components (ROM, SRAM, register files) in DSP using VHDL ModelSim.
• Developed a schematic and layout generator using SKILL script in Cadence environment,

automating design workflow and improving work efficiency.

The Hong Kong University of Science and Technology 

Master of Science• IC Design Engineering • 2005 – 2007 • GGA: A

The Hong Kong Polytechnic University

Bachelor of Engineering • Electronicand Information Engineering • 2001-2005 • 2nd Class Honours, Division I • GPA: 3.37