香港 的 Credo 职位

Implement basic DFT schemes including scan insertion boundary scan Mem BIST DRC clean ATPG and pattern simulation Support ATE bring-up and debug the ATE patterns for production flow Support logic BIST Memory BIST diagnosisfor yield improvement · ...

Duties: · Perform RTL to GDSII design flow, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, · EM/IR. · Requirements: · BSEE/MSEE with minimum 1-year of P& R experience by using SoC Encounter. · Fa ...

Digital design engineer duties include microarchitecture and design in Verilog/System Verilog define ASIC methodologies integrate complex IPs run block and chip level RTL verification gate-level netlist testing support back-end engineers timing-closure ECOs chip bring up validati ...

Duties include microarchitecture design in Verilog/System Verilog. · ...

+Duties Participate in a team to design and layout of high-speed ICs for optical fiber/wireline communications Design verification simulation and optimization for amplifier ADC/ DAC bandgap analog buffer LDO charge pump voltage reference PLL oscillator SerDes etc Create support d ...

Candidate will be part of core design team carrying the task to deliver the next generationsuper high-speed data IC for home networking,Candidate is responsible for SoC integration and verification.Travel may be required if necessary. · ...

Duties: Implement basicDFT schemes, including scan insertion, boundary scan, · Mem BIST, DRC clean. · Support ATE bring-up. · ...

Candidate will be part of core design team carrying the task to deliver the next generations super high-speed data IC for home networking Candidate is responsible for SoC integration and verification Travel may be required if necessary Requirements Bachelor degree or above in Ele ...

Duties: Perform RTL to GDSII design flow including floor planning power grid design place and route clock tree synthesis timing closure powersignal integrity signoff EM/IR. Participate in next generation physical design methodology and flow development. · ...

Design and layout of high-speed ICs for optical fiber/wireline communications. · ...